BLDC Gate Driver Selection: Dead Time, Bootstrap and Fault Response

Engineering note. This guide is published by the Sankey engineering content team for OEM planning. It explains the design decisions and evidence a project team should review; component datasheets, the intended end product, target-market requirements, and controlled laboratory testing remain the source of truth for a released design.

The gate driver converts control logic into switching behavior. Its selection and layout determine whether the power stage switches predictably through supply changes, startup, load steps, faults, and temperature.

What this decision changes

Driver architecture affects the practical switching speed, shoot-through margin, bootstrap supply behavior, fault latency, controller interface, layout constraints, and the evidence needed to support a reliable power-stage release.

Start with measurable inputs

List the MOSFET gate charge at the intended drive voltage, PWM frequency range, bus voltage, required fault response, high-side on-time, available bias rails, MCU logic level, expected temperature, and the physical distance between driver and MOSFET gates.

Engineering review method

Match the driver output capability to the required gate transition rather than to a headline current value. Review programmable or fixed dead time against measured propagation delays, then inspect bootstrap refresh conditions, undervoltage lockout, desaturation or over-current interfaces where used, and the return path for gate-drive current.

Evidence to keep with the design

Capture high- and low-side gate voltage, switch-node behavior, dead-time interval, fault-to-gate-disable timing, and bootstrap voltage during the longest expected high-side duty condition. Keep the probe method and layout revision with the record.

Failure paths to challenge early

Poorly controlled dead time can create shoot-through or unnecessary body-diode loss. Long gate loops, shared power returns, unverified bootstrap refresh, and a fault signal that reaches the MCU but not the gate driver quickly enough are recurring design risks.

Before prototype release

Release the driver arrangement only after normal switching and controlled fault tests demonstrate the intended gate state. Document gate-resistor values, driver configuration straps, fault polarity, recovery rules, and approved alternates.

Questions an OEM team should close

What is the measured interval between a fault condition and power-stage disable?
Can the bootstrap supply support the intended maximum high-side duty cycle?
Does the physical layout preserve the gate-drive return path assumed by the design?